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A 52-Gb/s ADC-Based PAM-4 Receiver With Comparator-Assisted 2-bit/Stage SAR ADC and Partially Unrolled DFE in 65-nm CMOS.
Shiva Kiran
Shengchang Cai
Ying Luo
Sebastian Hoyos
Samuel Palermo
Published in:
IEEE J. Solid State Circuits (2019)
Keyphrases
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analog to digital converter
high speed
image sensor
decision feedback
low power
low cost
image reconstruction
cmos image sensor
computer simulation
single chip
received signal
analog vlsi