A 128∶2048/1536 point FFT hardware implementation with output pruning.
Tuba AyhanWim DehaeneMarian VerhelstPublished in: EUSIPCO (2014)
Keyphrases
- hardware implementation
- signal processing
- efficient implementation
- software implementation
- image processing algorithms
- dedicated hardware
- hardware design
- hardware architecture
- fpga implementation
- search space
- fast fourier transform
- pipeline architecture
- fourier transform
- field programmable gate array
- image binarization
- neural network
- parallel architecture
- memory management
- floating point
- pruning method
- image processing
- information systems
- fourier transformation
- data mining