A Parametric Model Checking Approach for Real-Time Systems Design.
Chaiwat SathawornwichitTakuya KatayamaPublished in: APSEC (2005)
Keyphrases
- model checking
- real time systems
- timed automata
- temporal logic
- formal verification
- real time embedded
- formal methods
- embedded systems
- temporal properties
- reactive systems
- formal specification
- model checker
- distributed systems
- automated verification
- reachability analysis
- concurrent systems
- epistemic logic
- finite state
- modal logic
- asynchronous circuits
- pspace complete
- verification method
- symbolic model checking
- architectural model
- process algebra
- design patterns
- petri net
- case study