DP lower bounds for equivalence-checking and model-checking of one-counter automata.
Petr JancarAntonín KuceraFaron MollerZdenek SawaPublished in: Inf. Comput. (2004)
Keyphrases
- model checking
- lower bound
- finite state
- timed automata
- finite state machines
- verification method
- temporal logic
- dynamic programming
- formal verification
- model checker
- symbolic model checking
- temporal properties
- automated verification
- formal specification
- np hard
- formal methods
- objective function
- computation tree logic
- process algebra
- reachability analysis
- partial order reduction
- optimal solution
- pspace complete
- tree automata
- reactive systems
- transition systems
- epistemic logic
- linear temporal logic
- bounded model checking
- asynchronous circuits
- concurrent systems
- planning domains
- modal logic
- np complete