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A programmable delay-locked loop based clock multiplier.
Sungken Lee
Geontae Park
Hyungtak Kim
Jongsun Kim
Published in:
ISOCC (2012)
Keyphrases
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low cost
high speed
power consumption
floating point
hardware implementation
general purpose
type ii
critical path
website
optimal solution
feedback loop
computer vision
end to end
fixed point
low power
artificial intelligence
information retrieval
machine learning
real time