A layered QC-LDPC decoder architecture for high speed communication system.

Chiu-Wing Sham Xu Chen Wai Man Tam Yue Zhao Francis Chung-Ming Lau

Published in: APCCAS (2012)

Keyphrases

high speed
ldpc codes
low density parity check
real time
turbo codes
fpga implementation
distributed source coding
distributed video coding
error correction
distributed systems
end to end
low complexity
decoding algorithm