CMOS Latch Using Quad for High-Speed Comparators.
Venkatesh AcharyaT. Lakshmi ViswanathanThayamkulangara R. ViswanathanPublished in: IEEE Trans. Circuits Syst. II Express Briefs (2007)
Keyphrases
- high speed
- low power
- power consumption
- single chip
- real time
- cmos technology
- frame rate
- low cost
- power reduction
- vlsi circuits
- ultra low power
- digital signal processing
- focal plane
- high speed networks
- image sequences
- database systems
- sorting algorithms
- power dissipation
- neural network
- delay insensitive
- nm technology
- image sensor
- parallel processing
- case study
- learning algorithm
- data sets