A 14bit 500MS/s 85.62dBc SFDR 66.29dB SNDR SHA-less pipelined ADC with a stable and high-linearity input buffer and aperture-error calibration in 40nm CMOS.
Mingliang ChenKeke WuYupeng ShenZhiyu WangHua ChenJiarui LiuFaxin YuPublished in: IEICE Electron. Express (2021)