Parent node discovery time reduction algorithm for low-power wireless sensor networks.
Kota TsuchieTaketsugu YaoYuki KuboNobuyuki NakamuraMasanori NozakiPublished in: ICUFN (2017)
Keyphrases
- low power
- wireless sensor networks
- power consumption
- low cost
- high speed
- energy efficiency
- single chip
- energy efficient
- energy consumption
- sensor nodes
- sensor networks
- high power
- routing algorithm
- digital signal processing
- wireless transmission
- energy dissipation
- logic circuits
- gate array
- image sensor
- data transmission
- low power consumption
- resource constrained
- base station
- vlsi circuits
- multi hop
- power dissipation
- cmos technology
- power saving
- vlsi architecture
- digital camera
- delay insensitive
- data center
- signal processing
- signal processor
- real time