Design and Implementation of High Speed Arithmetic Coder Architecture of JPEG2000 on Reconfigurable FPGA.
M. F. EbianE. ElsehleyA. E. ElhenawyPublished in: IWCIA Special Track on Applications (2008)
Keyphrases
- hardware implementation
- fpga implementation
- reconfigurable hardware
- hardware architecture
- high speed
- field programmable gate array
- xilinx virtex
- hardware design
- fpga technology
- fpga device
- hardware software co design
- low cost
- hardware architectures
- software implementation
- hardware software
- efficient implementation
- dedicated hardware
- parallel architecture
- low power
- arithmetic coder
- single chip
- image processing algorithms
- systolic array
- dynamic reconfiguration
- processing elements
- power reduction
- real time
- embedded systems
- optical flow
- image processing