Network-on-Chip interconnect for pairing-based cryptographic IP cores.
Tom EnglishEmanuel M. PopoviciMaurice KellerWilliam P. MarnanePublished in: J. Syst. Archit. (2011)
Keyphrases
- network on chip
- power dissipation
- interconnection networks
- power consumption
- routing algorithm
- multi processor
- multi core processors
- low power
- smart card
- network simulator
- multistage
- parallel algorithm
- fault tolerant
- ip networks
- high speed
- cmos technology
- data transfer
- digital signal processing
- design methodology
- message passing
- real time
- end to end
- communication networks
- shortest path
- parallel programming
- ad hoc networks