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A 600-μm² Ring-VCO-Based Hybrid PLL Using a 30-μW Charge-Sharing Integrator in 28-nm CMOS.
Shiheng Yang
Jun Yin
Tailong Xu
Taimo Yi
Pui-In Mak
Qiang Li
Rui Paulo Martins
Published in:
IEEE Trans. Circuits Syst. II Express Briefs (2021)
Keyphrases
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cmos technology
silicon on insulator
high speed
power consumption
nm technology
charge coupled devices
low power
neural network
information sharing
learning algorithm
metal oxide semiconductor
knowledge sharing
information systems
multiple users
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analog vlsi
data sharing
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