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Reducing the Communication Bottleneck via On-Chip Cosimulation of Gate-Level HDL and C-Models on a Hardware Accelerator.

Alexander MailiChristian StegerReinhold WeissRob QuigleyDamian Dalton
Published in: ISVLSI (2005)
Keyphrases
  • low cost
  • vlsi implementation
  • image processing
  • high speed
  • data acquisition
  • real time
  • probabilistic model
  • hardware design