Partitioning FPGA-Optimized Systolic Arrays for Fun and Profit.
Long Chung ChanGurshaant MalikNachiket KaprePublished in: FPT (2019)
Keyphrases
- distributed memory
- parallel architecture
- systolic array
- hardware implementation
- high speed
- decision making
- arbitrary size
- computer games
- low cost
- field programmable gate array
- evolutionary algorithm
- graph partitioning
- neural network
- data sets
- principal direction
- dedicated hardware
- real time image processing
- partitioning algorithm
- software implementation
- hardware architecture
- hardware design
- data acquisition