Reducing the frequency of tag compares for low power I-cache design.

Ramesh Panwar David A. Rennels

Published in: ISLPD (1995)

Keyphrases

low power
low cost
single chip
power consumption
vlsi architecture
low power consumption
power reduction
logic circuits
high speed
gate array
digital signal processing
vlsi circuits
cmos technology
power dissipation
design process
real time
high power
mixed signal
nm technology