A Low-Power Charge-Domain Bit-Scalable Readout System for Fully-Parallel Computing-in-Memory Accelerators.
Wei MaoFuyi LiJun LiuRui XiaoKejie HuangYongfu LiHao YuYan LiuGenquan HanPublished in: IEEE Trans. Circuits Syst. II Express Briefs (2024)
Keyphrases
- low power
- parallel computing
- single chip
- power consumption
- computing systems
- high speed
- low cost
- computing platform
- field programmable gate array
- parallel programming
- commodity hardware
- multithreading
- massively parallel
- clock frequency
- analog to digital converter
- power dissipation
- high performance computing
- shared memory
- processing units
- digital signal processing
- map reduce
- graphics processing units
- low power consumption
- computer architecture
- memory access
- cmos technology
- image processing
- nm technology
- real time
- main memory
- parallel computers
- signal processing
- probabilistic model
- mixed signal