A reconfigurable sense amplifier with 3X offset reduction in 28nm FDSOI CMOS.
Mahmood KhayatzadehFabio FrustaciDavid T. BlaauwDennis SylvesterMassimo AliotoPublished in: VLSIC (2015)
Keyphrases
- low cost
- power reduction
- power consumption
- low power
- cmos technology
- high speed
- high power
- silicon on insulator
- reconfigurable architecture
- metal oxide semiconductor
- nm technology
- hardware implementation
- analog vlsi
- reduction method
- delay insensitive
- power supply
- high sensitivity
- data reduction
- rough sets
- floating gate
- systolic array
- multi objective evolutionary
- cmos image sensor
- image sequences