Architecture design of low-power motion estimation based on DHS-NPDS for H.264/AVC.
Yunbi ChenZhengdong LiLi GuoJinsheng XieLong ZhaoPublished in: Sci. China Inf. Sci. (2012)
Keyphrases
- low power
- motion estimation
- video coding
- deblocking filter
- inter frame
- video compression standard
- coding efficiency
- variable block size
- rate distortion
- power consumption
- low complexity
- low cost
- high speed
- macroblock
- motion vectors
- motion compensation
- motion compensated
- video coding standard
- computational complexity
- video compression
- rate control
- optical flow
- video sequences
- single chip
- reference frame
- video codec
- block matching
- bit rate
- digital signal processing
- mode decision
- vlsi architecture
- video quality
- compression efficiency
- image sequences
- error propagation
- super resolution
- compressed domain
- spatial domain
- logic circuits
- computer vision
- image sensor
- vlsi circuits
- bitstream
- cmos technology
- scalable video coding
- transform domain
- intra prediction
- low power consumption
- image coding
- power reduction
- delay insensitive
- coding method
- distributed video coding