Power-aware high level evaluation model of interconnect length of on-chip memory network topology.
Xiaojun WangFeng ShiYizhuo WangHong ZhangXu ChenWen-Fei FuPublished in: Int. J. Comput. Sci. Eng. (2018)
Keyphrases
- network topology
- evaluation model
- power dissipation
- power consumption
- high level
- low power
- high speed
- ad hoc networks
- evaluation method
- network structure
- artificial immune network
- cmos technology
- memory subsystem
- energy conservation
- ibm eservertm
- routing protocol
- multithreading
- network topologies
- protein protein interactions
- bp neural network
- fuzzy analytic hierarchy process
- clock frequency
- fuzzy theory
- ibm power processor
- mobile ad hoc networks
- analytic hierarchy process
- high bandwidth
- real time
- university libraries
- control system
- optimization algorithm
- fuzzy comprehensive evaluation
- complex networks
- energy saving