Pipelined ADPCM Compression for HDR Synthesis on an FPGA.
Masahiro NishimuraTaito ManabeYuichiro ShibataPublished in: IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (2024)
Keyphrases
- parallel architecture
- image compression
- hardware implementation
- high dynamic range
- compression rate
- data compression
- signal processing
- high speed
- compression algorithm
- compression ratio
- field programmable gate array
- compression scheme
- fpga implementation
- real time
- low cost
- verilog hdl
- hardware design
- data flow
- lossless compression
- texture synthesis
- tone mapping
- real time image processing
- high dynamic range images
- pixel values
- power consumption
- data acquisition
- multiresolution
- program synthesis
- computational complexity
- reconfigurable hardware
- parallel hardware
- multiscale