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Column-selection-enabled 8T SRAM array with ~1R/1W multi-port operation for DVFS-enabled processors.
Sang Phill Park
Soo Youn Kim
Dongsoo Lee
Jae-Joon Kim
W. Paul Griffin
Kaushik Roy
Published in:
ISLPED (2011)
Keyphrases
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parallel processing
power reduction
real time
parallel algorithm
data structure
low cost
data management
power consumption