A 1.56GHz wide-tuning all digital FBAR-based PLL in 0.13µm CMOS.

Julie R. Hu Richard C. Ruby Brian P. Otis

Published in: CICC (2010)

Keyphrases

high speed
circuit design
cmos image sensor
power consumption
low power
low cost
wide range
mixed signal
parameter tuning
data sets
delay insensitive
rule selection
digital curves
analog vlsi
cmos technology
power supply
multimedia
neural network