An area efficient low power ECoG front-end chip for digitalized subdural grid.

Chenjie Dong Han Jin IkHwan Kim Chenyu Wang Yajie Qin Li-Rong Zheng

Published in: ASICON (2017)

Keyphrases

low power
high speed
low cost
single chip
power consumption
low power consumption
mixed signal
cmos technology
power dissipation
signal processor
high power
power reduction
ultra low power
real time
vlsi circuits
logic circuits
digital signal processing
vlsi architecture
gate array
image sensor
wireless transmission