A circuit approach to LTL model checking.
Koen ClaessenNiklas EénBaruch SterinPublished in: FMCAD (2013)
Keyphrases
- model checking
- temporal logic
- bounded model checking
- formal verification
- formal specification
- finite state machines
- model checker
- temporal properties
- asynchronous circuits
- linear time temporal logic
- linear temporal logic
- partial order reduction
- computation tree logic
- automated verification
- verification method
- transition systems
- reachability analysis
- finite state
- symbolic model checking
- epistemic logic
- formal methods
- concurrent systems
- pspace complete
- process algebra
- timed automata
- ordered binary decision diagrams