A 3.2-GHz 0.3/0.5 V 16-nm FinFET I/O Buffer With Low-Power PVT Compensation Circuit.
Tzung-Je LeeJi-Hau ChiouPublished in: ISCAS (2024)
Keyphrases
- low power
- cmos technology
- clock frequency
- power consumption
- clock gating
- high speed
- power reduction
- virtual memory
- low cost
- power dissipation
- low voltage
- nm technology
- replacement policy
- logic circuits
- power saving
- main memory
- wireless transmission
- mixed signal
- single chip
- digital signal processing
- vlsi circuits
- high power
- vlsi architecture
- gate array
- power management
- real time
- image sensor
- low power consumption
- operating system
- parallel processing
- file system
- hardware and software