Bipartition Architecture for Low Power JPEG Huffman Decoder.
Shanq-Jang RuanWei-Te LinPublished in: Asia-Pacific Computer Systems Architecture Conference (2007)
Keyphrases
- low power
- vlsi architecture
- fpga implementation
- power consumption
- low density parity check
- high speed
- low cost
- cmos technology
- mixed signal
- nm technology
- single chip
- image compression
- real time
- decoding process
- low complexity
- low power consumption
- image coding
- hardware implementation
- ldpc codes
- data flow
- logic circuits
- arithmetic coder
- coded images
- power dissipation
- field programmable gate array
- decoding algorithm
- arithmetic coding
- jpeg images
- lossy compression
- low bit rate
- discrete cosine transform
- error concealment
- compression ratio
- compression algorithm
- signal processing
- motion estimation
- video sequences