Device-Circuit Optimization for Minimal Energy and Power Consumption in CMOS Random Logic Networks.
Pankaj PantVivek DeAbhijit ChatterjeePublished in: DAC (1997)
Keyphrases
- power consumption
- energy efficiency
- low power
- energy saving
- power dissipation
- power reduction
- battery powered
- delay insensitive
- cmos technology
- energy management
- ultra low power
- clock gating
- battery life
- save energy
- power management
- power saving
- chip design
- nm technology
- flip flops
- data center
- low voltage
- energy efficient
- high speed
- circuit design
- network structure
- social networks
- packet delivery
- silicon on insulator
- low power consumption
- asynchronous circuits
- real time
- cluster head
- low cost