An effective approach for model checking SystemC designs.
Razieh BehjatiHamideh SabouriNiloofar RazaviMarjan SirjaniPublished in: ACSD (2008)
Keyphrases
- model checking
- temporal logic
- automated verification
- formal specification
- model checker
- temporal properties
- partial order reduction
- verification method
- finite state machines
- transition systems
- finite state
- reachability analysis
- timed automata
- symbolic model checking
- process algebra
- formal verification
- bounded model checking
- epistemic logic
- pspace complete
- computation tree logic
- concurrent systems
- formal methods
- abstract interpretation
- linear temporal logic
- planning domains
- satisfiability problem