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An optimal and processor efficient parallel sorting algorithm on a linear array with a reconfigurable pipelined bus system.
Min He
Xiaolong Wu
Si-Qing Zheng
Published in:
Comput. Electr. Eng. (2009)
Keyphrases
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linear array
dynamic programming
optimal solution
parallel implementation
computational complexity
worst case
parallel processing
hardware implementation
sorting algorithms
np hard
low cost
high speed
parallel architecture
signal processing
single processor