A 150MHz-400MHz DLL-Based Programmable Clock Multiplier with -7OdBc Reference Spur in 0.18um CMOS.

Prabir C. Maulik Douglas A. Mercer

Published in: CICC (2006)

Keyphrases

high speed
fpga device
power consumption
low power
general purpose
high frequency
hardware implementation
cmos technology
image processing
low cost
floating point