Parallelizing Synthesis from Temporal Logic Specifications by Identifying Equicontrollable States.
Sumanth DathathriIoannis FilippidisRichard M. MurrayPublished in: ISRR (2017)
Keyphrases
- temporal logic
- concurrent systems
- model checking
- transition systems
- model checker
- reactive systems
- bounded model checking
- formal specification language
- finite state machines
- modal logic
- satisfiability problem
- formal specification
- linear temporal logic
- automata theoretic
- dynamic constraints
- verification method
- computation tree logic
- mazurkiewicz traces
- belief revision
- temporally extended goals
- temporal knowledge
- formal verification
- video sequences
- specification language
- np complete
- software engineering