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Design of gate-leakage-based timer using an amplifier-less replica-bias switching technique in 55-nm DDC CMOS.
Atsuki Kobayashi
Yuya Nishio
Kenya Hayashi
Shigeki Arata
Kiichi Niitsu
Published in:
ASP-DAC (2019)
Keyphrases
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cmos technology
nm technology
design process
low power
power consumption
circuit design
metal oxide semiconductor
real time
control system
low cost
peer to peer
x ray
parallel processing
design principles
single chip
high power