An average low offset comparator for 1.25 Gsample/s ADC in 0.18 μm CMOS.

Nikolas Stefanou Sameer R. Sonkusale

Published in: ICECS (2004)

Keyphrases

high speed
analog to digital converter
standard deviation
high levels
data structure
low power
highly correlated
single chip
delay insensitive
case study
expert systems
low cost
power supply