Power-mode-aware Memory Subsystem Optimization for Low-power System-on-Chip Design.
Manuel StrobelMartin RadetzkiPublished in: ACM Trans. Embed. Comput. Syst. (2019)
Keyphrases
- power consumption
- low power
- power dissipation
- single chip
- low power consumption
- power reduction
- logic circuits
- memory subsystem
- high speed
- low cost
- high power
- cmos technology
- ultra low power
- digital signal processing
- power management
- mixed signal
- energy efficiency
- gate array
- design process
- hardware and software
- embedded systems
- image sensor
- design methodology
- computational complexity
- real time