Hardware architectures for Successive Cancellation Decoding of Polar Codes
Camille LerouxIdo TalAlexander VardyWarren J. GrossPublished in: CoRR (2010)
Keyphrases
- hardware architectures
- decoding algorithm
- error control
- reed solomon
- parity check
- ldpc codes
- low density parity check
- computational power
- joint source channel
- error correction
- error correcting
- decoding complexity
- hardware architecture
- fourier transform
- rotation invariant
- turbo codes
- image transmission
- frequency domain
- rate allocation
- reed solomon codes
- decoding process
- polar coordinates
- soft decision
- channel coding
- zernike moments
- coding scheme
- space time block
- belief propagation