Timing-aware clock gating of pulsed-latch circuits for low power design.
Zong-Han YangTsung-Yi HoPublished in: VLSI-DAT (2013)
Keyphrases
- low power
- power reduction
- power consumption
- power dissipation
- clock gating
- logic circuits
- high speed
- low cost
- single chip
- cmos technology
- digital signal processing
- vlsi architecture
- low power consumption
- mixed signal
- power saving
- vlsi circuits
- energy efficiency
- power management
- nm technology
- image sensor
- delay insensitive
- gate array
- asynchronous circuits
- ultra low power
- flip flops
- real time
- signal processing
- image processing