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Evaluation of low power consumption network on chip routing architecture.
T. S. Arulananth
M. Baskar
Udhaya Sankar S. M
R. Thiagarajan
G. Arul Dalton
Pasupuleti Raja Rajeshwari
Aruru Sai Kumar
Suresh A
Published in:
Microprocess. Microsystems (2021)
Keyphrases
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network on chip
routing algorithm
low power consumption
real time
routing protocol
low cost
power consumption
multi processor
wireless sensor networks
low power
network simulator
shortest path
database
ad hoc networks
storage devices
end to end
general purpose
multipath