An Energy-Efficient Hybrid SAR-VCO ΔΣ Capacitance-to-Digital Converter in 40-nm CMOS.
Arindam SanyalNan SunPublished in: IEEE J. Solid State Circuits (2017)
Keyphrases
- high speed
- analog to digital converter
- low power
- metal oxide semiconductor
- cmos technology
- low voltage
- data conversion
- mixed signal
- circuit design
- power consumption
- wireless sensor networks
- synthetic aperture radar
- nm technology
- low cost
- energy efficient
- cmos image sensor
- energy efficiency
- sar images
- power dissipation
- control method
- image reconstruction
- parameter estimation
- unit length
- image sensor
- power supply
- single chip
- sensor networks
- real time