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Efficient scan-based BIST scheme for low power testing of VLSI chips.
Malav Shah
Published in:
ISLPED (2006)
Keyphrases
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low power
high speed
power consumption
single chip
low cost
vlsi circuits
vlsi architecture
gate array
power dissipation
high power
low power consumption
mixed signal
wireless transmission
digital signal processing
signal processing
cmos technology
logic circuits
chip design