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Low-power digital PLL with one cycle frequency lock-in time and large frequency-multiplication factor for advanced power management.
Rafael Fried
Ziv Azmanov
Published in:
ICECS (1996)
Keyphrases
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power consumption
low power
power management
high speed
energy efficiency
mixed signal
low cost
vlsi circuits
energy saving
wireless transmission
logic circuits
power reduction
high power
nm technology
image processing
vlsi architecture
digital signal processing
single chip
ambient intelligence