Enhancing the Hardware Pipelining Optimization Technique of the SHA-3 via FPGA.
Argyrios SiderisMinas DasygenisPublished in: Comput. (2023)
Keyphrases
- field programmable gate array
- hardware implementation
- hardware architecture
- low cost
- parallel hardware
- hardware design
- software implementation
- real time
- single chip
- reconfigurable hardware
- hardware architectures
- fpga implementation
- low power consumption
- dedicated hardware
- xilinx virtex
- fpga technology
- fine grain
- image processing algorithms
- embedded systems
- data acquisition
- digital signal processing
- hardware description language
- hardware and software
- hardware software
- general purpose processors
- massively parallel
- programmable logic
- fpga hardware
- low power
- pipelined architecture
- fpga device
- neural network
- real time image processing
- parallel architecture
- computational power
- computing systems
- personal computer
- signal processing
- high speed
- image processing
- parallel computing
- systolic array
- parallel processing
- gate array