A 24.6-29.6GHz Hybrid Sub-Sampling PLL with Tri-State Integral Path Achieving 44fs Jitter and -254.8dB FOM in 28nm CMOS.
Zhongkai WangMinsoo ChoiPaul KwonZhaokai LiuBozhi YinKyoungtae LeeKwanseo ParkAyan BiswasJaeduk HanSijun DuElad AlonPublished in: ISCAS (2024)