A compliance current circuit with nanosecond response time for ReRAM characterization.

Qingjiang Li Jinling Xing Zhaolin Sun Fei Jing Hui Xu

Published in: ISCAS (2017)

Keyphrases

response time
high speed
scheduling algorithm
low cost
query execution
circuit design
database
data sets
neural network
information systems
evolutionary algorithm
multi dimensional
network latency
short circuit