Low Power Scheduling of DAGs to Minimize Finish Times.
Sanjeev BaskiyarKiran Kumar PalliPublished in: HiPC (2006)
Keyphrases
- low power
- power consumption
- low cost
- high speed
- scheduling problem
- single chip
- high power
- directed acyclic graph
- scheduling algorithm
- wireless transmission
- digital signal processing
- mixed signal
- vlsi circuits
- resource constraints
- parallel machines
- low power consumption
- delay insensitive
- general purpose
- real time
- cmos technology
- logic circuits
- vlsi architecture