Simple Bounded LTL Model Checking.
Timo LatvalaArmin BiereKeijo HeljankoTommi A. JunttilaPublished in: FMCAD (2004)
Keyphrases
- model checking
- temporal logic
- finite state machines
- formal verification
- automated verification
- formal specification
- bounded model checking
- symbolic model checking
- finite state
- model checker
- linear temporal logic
- temporal properties
- reachability analysis
- pspace complete
- partial order reduction
- transition systems
- epistemic logic
- computation tree logic
- formal methods
- verification method
- process algebra
- timed automata
- reactive systems
- asynchronous circuits
- modal logic
- linear time temporal logic