High-Level Synthesis Implementation of an Accurate HEVC Interpolation Filter on an FPGA.

Panu Sjövall Matti Rasinen Ari Lemmetti Jarno Vanne

Published in: NorCAS (2021)

Keyphrases

high level synthesis
parallel architecture
interpolation filter
hardware implementation
parallel processing
efficient implementation
case study
motion compensation
message passing
video compression
design space exploration