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Structured Weight Matrices-Based Hardware Accelerators in Deep Neural Networks: FPGAs and ASICs.
Caiwen Ding
Ao Ren
Geng Yuan
Xiaolong Ma
Jiayu Li
Ning Liu
Bo Yuan
Yanzhi Wang
Published in:
ACM Great Lakes Symposium on VLSI (2018)
Keyphrases
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neural network
weight matrices
field programmable gate array
weight matrix
pattern recognition
embedded systems
hardware implementation
application specific integrated circuits
pairwise
clustering algorithm
efficient implementation
computing systems
image processing algorithms