A compact, low power AES core on 180nm CMOS process.

Van-Lan Dao Van-Phuc Hoang Anh-Thai Nguyen Quy-Minh Le

Published in: ICICDT (2016)

Keyphrases

low power
cmos technology
power consumption
low cost
high speed
nm technology
wireless transmission
single chip
logic circuits
low power consumption
high power
power reduction
vlsi architecture
vlsi circuits
digital signal processing
delay insensitive
multi channel
real time