A novel SRAM - STT-MRAM hybrid cache implementation improving cache performance.
Odilia CoiGuillaume PatrigeonSophiane SenniLionel TorresPascal BenoitPublished in: NANOARCH (2017)
Keyphrases
- prefetching
- random access memory
- query processing
- data access
- design considerations
- hit rate
- replacement policy
- cache management
- power consumption
- shared memory multiprocessor
- efficient implementation
- main memory
- memory access
- memory subsystem
- cache replacement
- embedded processors
- semantic caching
- shared memory multiprocessors
- cache misses
- memory hierarchy
- web caching
- memory management
- access patterns
- low power
- response time
- sensor networks