A Low Power Sample-and-Hold Circuit with Improved Dynamic Bias for Pipelined ADC.
Xiaodan ZhouZehao LiYujie WangXiong ZhouShiheng YangJiaxin LiuQiang LiPublished in: APCCAS (2021)
Keyphrases
- low power
- high speed
- logic circuits
- power consumption
- single chip
- low cost
- cmos technology
- delay insensitive
- power reduction
- vlsi circuits
- gate array
- high power
- vlsi architecture
- power dissipation
- wireless transmission
- wide dynamic range
- mixed signal
- digital signal processing
- nm technology
- real time
- power saving
- low power consumption
- image sensor
- data flow
- signal processor
- ultra low power
- sigma delta
- hardware and software